Translation of "Relative addressing" in German

Apart from providing relative addressing of the cursor by the deflection of the cursor control device, it is also possible to derive a relative cursor speed in relation to deflection.

If in addition to individual symbols, symbol sequences also, can stand for the characters, then the number of symbols per character is advantageously stored as information, and the aforementioned relative addressing is effected through additional consideration of the character length.

By using the relative addressing with STD and LDD time increasing gets rather simple.

If he wants to generate position independent programs (which can be loaded and executed at any address without relocation), then he should only use relative addressing.

Both requirements can be satisfied without problems, as these processors have the needed addressing modes (relative addressing, indirect addressing with any offset value, etc.).

In most mechanisms we have a relative addressing scheme (e.g. next, previous, first row, last row,…) and in some we have an absolute addressing.

It is assumed that initially no relative address is stored.

The reading out of the relative address is controlled by means of a coefficient memory counter KMCT.

We will need to address relative competitiveness inside the Euro area and in the wider EU.

This involves relative addresses for the period of non-conference-relevant signals in the respective pulse bracket.

The delayed relative address adrv can in this case be written into the address memory DPRAM as a function of a control signal zw.

When relative addresses are being used, the pattern depends on the current position within the document.

This formula only can find the first relative cell address which matches the lookup value.

This Function translates the RBA (Relative Block Address) to ABA (Absolute Block Address).

The central processing unit provided in a PCM time-division multiplex communication network assigns relative addresses to the conference related stations, which addresses are necessary for setting up and maintaining the conference connection.

Now, the process according to the invention is advantageously carried out in such a way that these relative addresses are also used for the temporary storage of the received PCM signals and of the partial sums as well as for transmitting the partial sums.

At the start of the next succeeding pulse bracket, the partial sum signals stored temporarily in the transmitting storage registers 114 and 115 may be read out under control by the logic control circuit 103 and with the use of the relative address signals already mentioned, and by way of a compressor 116 provided in common for both processing channels I and II can be fed to a transmitting synchronizing storage register 117, while at the same time further new PCM signals can be received from the conference-related connectors.

The compressor 116 converts the 12-digit linear words fed to it into nonlinear eight-digit signal words which are synchronized with the transmitting time slot. Sequence clock pulse TCL in the transmitting synchronizing storage register 117, and, in connection with the time slot assigned and set for the respective relative address, is read out by way of an OR element 118 and transmitted by way of the multiplex line 107 to the conference-related stations; i.e., the stations actually involved in a given conference.

As the setting-up information of the received pulse train phase is further processed in a computer, this is transferred as a relative address PAR.

This further development requires only two relatively small registers, which store the relative addresses and time slot set commands emitted by the central processing unit in time sequence.