Translation of "Watchdog timer" in German

This sets the watchdog timer 18 to 3.2 seconds and activates the HSYNC signal.

The device was woken from the sleep state by the watchdog timer.

An appropriate software or also a watchdog timer may be used for monitoring.

The deactivation of the watchdog timer WD can also be carried out differently than in the manner described above.

A RESET will be initialised through the integrated watchdog-timer.

The watchdog timer (step 24) sets the switching moments within the sequence.

A watchdog timer remains active, in order to wake the control unit CPU after a defined sleep interval.

As an alternative, it might be provided that a clock signal with a lower frequency is fed to the watchdog timer.

The automatic deactivation of the watchdog timer that is carried out by the OCDS module used in the present case has a number of advantages over such processes.

Data Sheet MC 68 F 333 TS/D, Motorola 1992, already discloses a microcomputer which has, apart from the central processing unit, a programmable, non-volatile memory (flash EEPROM), input/output components, a monitoring circuit (watchdog timer), and also a volatile memory (code RAM), into which there can be written program data which can be accessed by the instruction counter of the central processing unit.

The reference numeral 12 denotes a monitoring circuit, which has also become known in the literature by the term watchdog timer.

Finally, the reset element is connected via a third control input, which has an OR relation to the two other inputs, to the output of a watchdog timer 121 .

The watchdog timer 121 furthermore activates the resetting element, thus shutting down the complete HF or the individual electrode feed lines if irregularities in the data transmission are detected.

Counter CNT 80, which is made up of the two 8-bit counters CNT_HB 81 and CNT_LB 80, thus functions as a 16-bit counter which is incremented by 1 after every four decrement steps of watchdog timer WDCNT 79 .

Otherwise, the algorithm proceeds to step 342, which also directs the algorithm to steps 338 and 310 if the transmission is outside of a "working range" which is preferably defined as gears 4-10, else the algorithm proceeds to step 344, where the watchdog timer is reset, as in previously described step 312.

If not armed, then step 516 repetitively loops back, and eventually, watchdog timer 46 times out and the algorithm is hardware shifted to the beginning of main loop 300.

If a long time watchdog timer has timed out, this is signaled as status 250 with the LED 108 flashing red.

The long time watchdog timer times out when the data center has not been contacted for a long time, for example in order to reload a credit.

During sleep the processor clock is shut off, and only the internal watchdog timer is running to periodically wake up the processor (about every 18ms).

It reduces design cycle time, component count, and bill of material (BOM) costs compared to discrete solutions by integrating 13 regulators, including 9 low-dropout linear regulators, real-time clock (RTC), backup battery charger, watchdog timer, flexible power sequencing and 8 general-purpose input/outputs (GPIOs).

The MIC826 is a low-current, ultra-small, voltage supervisor with manual reset input, watchdog timer, and active-high and active-low push-pull outputs.

Thanks to its additional functions such as Timer, Watchdog, survey of the outputs, and encode able Mini-Combicon screw-type terminal block, the board is specially suited for industrial applications.

To understand the importance of a software watchdog, let's look at what many existing systems use to recover from software faults: a hardware watchdog timer attached to the processor reset line.