Translation of "Kontrollregister" in English

Exporters must keep a register containing the following information:

Various operating modes, transmission frequencies and bit widths can be permanently stored in a control register.

In control port TCCR0B the timer is started with a prescaler value of 1.

She asked about various entries in the check register.

Various operating modes can be permanently set via the control register.

Exporters shall also cooperate in any checks which Member States may deem necessary and shall keep the registers for at least three years from the end of the current calendar year.

After a system reset and upon each watchdog reload, the check register 26 has the complement of the comparison value, which in this example is the number AAH, preallocated to it.

On one hand, this signal causes a switch 30 to be connected through so that the contents WDREL of the register 22 are loaded into the counter timer 20, and on the other hand it causes the control register 26 to have the complement of the comparison value, in this example the value AAH, preallocated to it.

If individual program routines are not executed, then the bit pattern in the check register 26 will not match the comparison value in the register 25.

The check register 26 is not affected by the watchdog reset, so that it can be subsequently evaluated by program, and program routines that are not executed can be ascertained in the process.

The signal RO# then returns to the "high state" only once all of the program routines have been executed and thus the check bits in the check register 26 have been set, and indeed have been set in the correct order.

More particularly, additional control registers are then also provided on the semiconductor substrate, whereby, for example, the sequence of the individual memory controllers on the bus is established and the master is designated.

After receipt of a message, in a time-controlled manner (after a preselected value on timer 844 has elapsed) or after triggering by another communication controller (e.g., controller 750 c) having an active interface “a” or by microprocessor 102 (triggering is performed by writing the configuration data such as memory area and data volume, to control register 838), routing engine 830 of a certain communication controller (e.g., communication controller 750 a) having active interface “a” independently controls sequential operations to transfer a message from a message memory 300 b or 300 c of another communication controller 750 b or 750 c or from memory area 802 of microcontroller 800 into a separate message memory 300 a:

They are, first of all, message handler 200 responsible for controlling the operational sequences, as well as two control registers 403 and 404 which, as shown, may be accommodated outside of message handler 200 in communication module 100, but may also be contained in message handler 200 itself.

They are, first of all, message handler 200 responsible for controlling the operational sequences, as well as two control registers 703 and 704 which, as shown, may be accommodated outside of message handler 200 in communication module 100, but may also be contained in message handler 200 itself.

These include, first, message handler 200, which is responsible for controlling the sequences, and two control registers 703 and 704, which may be accommodated outside of message handler 200 in communication module 100, as shown here, but may also be included in message handler 200 itself.

Host Controller Interface (HCI) provides a command interface to the baseband controller and link manager, and access to hardware status and control registers.

The first incident happened on February 18, 2011. My wife was looking through my check register demanding explanations of particular items.

In the control port TCCR0A of timer TC0 the CTC mode is set and both output pins are defined to toggle on compare match.

If such control registers do not exist, the designation of the master and establishing of the sequence of the memory controllers on the bus is established during initialization of the memory system by means of the following method: The initializing host system knows the size of the memory system and number of utilized memory controllers.

The memory controllers SCx are integrated here on the semiconductor substrate H. Additionally provided on the semiconductor substrate H is the control register KR, which contains for each memory controller SCx a field that contains the controller number Sx and the designation of the master M. These values are written into the control register KR during initialization of the memory system.

At manufacturing and working out of banknotes on the first place there is a protection against fakes. Along with the distinguishing marks (type of paper, dotted metal thread, check register, etc.), banknotes contain additional invisible signs, which can only be distinguished with the help of special equipment.