Translation of "Lesezyklus" in English

The clock signal SCLK is a constant LOW over the entire parallel read cycle.

Similarly, upon the serial read cycle, the serial data are driven by the corresponding slave.

The potential applied to the capacitor can, for example, be adjusted in each read cycle.

The shortest possible write cycle generally lasts at least as long as the minimum read cycle.

During the entire reading cycle 38, the BF line 25 has an applied reference voltage.

The recharging of this node has merely to be executed before the full termination of the read cycle.

This address substitution, however, is to occur only during the reading process from the second image memory RAM2, for this reason the slow clock pulse T2 whose pulse pause respectively temporally determines a read cycle is likewise offered to the address adder ADD.

It should also be noted that during a read cycle for the read-only memory, the release signal PREN must be present and the release signals SPEN and REGEN may not be effective.

This address substitution, however, is to occur only during the reading process from the second image memory RAM2, for this reason the slow clock pulse T2 whose pulse pause respectively temporally determines a read cycle is likewise offered to the address adder ADD.

When the picture is not frozen, the write-in cycle is used continuously but the read-out cycle is used only during the time when the compound picture appears (on the screen of television monitor 18) within the time interval per television picture.

During the course of this control cycle, a read cycle is first carried out in the counter reading memory ZSP1 according to the description of the address signals just supplied to it.

During the implementation of the read cycle, both the respective bit rate value as well as the allocated limit value are then supplied to the adder ADD for example by way of a register that is expanded in comparison to the register Reg2 illustrated in FIG. 2.

As explained below in detail, the second control device causes per write cycle of the video storage device 4 and per read cycle of the fifo storage device 3, respectively, re-storage of a plurality of data words from said first storage device 3 into the video storage device 4; the number of data words restored can vary from case to case, as explained below.

After this, there is performed a reset and read cycle as is also performed in the case of any voltage failure, after reinsertion or switching on of the supply voltage.

In the implementation of the described read cycle, both the respective bit rate value as well as the maximum counter reading associated thereto are supplied to the adder ADD1 for example, by way of a register expanded in comparison to the register Reg3 shown in FIG. 3.

Based on the representation of the virtual channel number contained in the cell header of this message cell, the memory area of the read-write memory RAM1 under consideration for the respective virtual connection is additionally driven for a read cycle via the multiplexer MUX from the decoder means DEC1.

In the Read cycle, the ILC line 15 is at high state and the gated inputs to input latches 14 are closed.

For the purpose of simplifying the technical interrelationships, it should be pointed out here, deviating from what was described above, that the read cycle of the holding memory H begins with the time slot Y4' and is terminated with the time slot Y3".

Since, simultaneously, the zero potential is applied to the second bit line Y as well as to the word line Z, the tunnel oxide of the non-selected memory cells are not loaded during a reading cycle.

As described above, the sense latch has been pre-set shortly after the beginning of the read cycle to the "1" stage associated with the longer internal access time.

At the beginning of the counting operation, all of the storage transistors in the storage matrix M as well as those in the main storage Hs, and in the course of an erase cycle, are set, for example, to lower threshold voltage (UDD)-values, which are to represent logic zeros. After this, there is performed a reset and read cycle as is also performed in the case of any voltage failure, after reinsertion or switching on of the supply voltage.

Furthermore, the micro controller MC reacts to the event “arrival of a second resource management cell RM(UER 2) transmitted in a second transmission direction UER 2 ” to the effect that the explicit transmission rate ECRx is first read from the second resource management cell RM(UER 2) transmitted in the second transmission direction UER 2, and then the second evaluation routine BWR 2 is started. Prior to this, however, the individualized-connection parameters Px required for execution must first be loaded from the non-volatile memory unit ROM into the volatile memory unit RAM in the course of a read cycle.

Upon a read access to the parallel bus system (parallel reading cycle) an address signal as well as control signals for the type of transfer are first of all set, these signals being driven by the master.

In the parallel reading cycle, the clock signal for a serial data access is preferably constant, for instance LOW (logical 0).

The magneto-optical drive may have a simple construction for both embodiments, because only one external magnetic field is required for the write and read-out cycle.

During a read cycle for reading out a data signal from a memory cell, for example, the relevant column line has an active mode.