Translation of "Prozessortakt" in English

The internal readout then takes place through the processor clock pulse.

This function limits the processor's speed to 0.8 GHz and turns off Turbo-Boost.

The clock rate is synchronous with the processor clock rate and corresponds to one period.

The controller's clock frequency is configurable with the constant clock.

Thanks to Turbo Boost, the processor rate can be raised to up to 3.1 GHz.

This kind of clock conditioning unit may include a frequency divider that is triggered by an externally inputtable processor clock.

The advantage is thereby that the four membership function values are already present in ordered form after a single processor clock.

The controller clock is sourced from an xtal of 3.2768Mhz on the XTAL1 and XTAL2 pins.

A computer with at least 800MHz processor clock is recommended for use with the micro-Keyer 2R/2R+.

According to an advantageous exemplary embodiment, the period of time during which the pulses of the clock generator are counted is set as a function of the processor clock rate.

The article entitled PCF84C640 specification, version 1.0 by J.C.P.M. Pijnenburg, published in the Philips Laboratory Report Number DPE 87221 of Nov. 16, 1987, discloses a generic microcomputer. In particular, attention is directed to page R21, FIG. 20 thereof, which shows a functional unit operating asynchronously with the processor clock rate and being controlled by a clock generator that is synchronizable by external signals, in this case a DOS (Display On Screen) unit.

In the circuit shown in the drawing, the frequency adjustment of the RC oscillator can be performed through the registers B1, B2, . . ., Bn by means of the central processing unit CPU. The processor clock rate, which is generated, for instance, by a quartz oscillator or a surface wave filler oscillator, can serve as a reference in this process.

The processor clock from the clock output 10 is divided in the example in the ratio 8:1 (this division ratio does not have any necessary relationship to the standard representation of messages in the form of bytes which each comprise 8 bits) by a clock divider 14 .

A linking device with at least two inputs and one output may also be provided, wherein one of the inputs is acted upon by the externally inputtable processor clock, and the at least one input can be connected to at least one output of the frequency divider.

In that case, the clock conditioning unit may include a switch device that typically switches an externally input processor clock to the CPU and that switches the clock furnished by the internal unit on to the CPU during a reading process in the EEPROM.

This mode is appropriate especially when the data transmitters do not supply the data in each clock pulse of the processor but instead only in every n th clock pulse.

The method presented here will define several different operational modes M for a digital logic semiconductor component: each operational mode M will be allocated a processor clock cycle TA with a specific clock frequency f and a limit temperature TG; when this temperature TG is reached, the operational mode M will change.

DESCRIPTION OF A PREFERRED EMBODIMENT As shown in FIG. 1, oscillator 3 which generates processor clock cycle TA will apply clock signal TS via circuitry 2 to the digital logic semiconductor component 1 controlling devices 4.

In the first embodiment, the current maximum is thereby connected to the output A and the current minimum is connected to the output D and the currently read-in value Wi is connected onto the outputs B and C. in a further processor clock, a first value Wi that does not correspond to the maximum or minimum value is connected onto the output A and a second value of Wi that does not correspond to the maximum or minimum value is connected onto the output B in order to determine the pointers MAX' and MIN' in the position registers P2 and P3, and thus to enable an order access to the holding elements L1-L4 via the pointers MAX, MAX', MIN' and MIN.

Finally, insofar as u is even-numbered, a last maximum and a last minimum are formed in a last processor clock from the two last membership function values.

Due to the restrictions of the hardware, in which particular mention should be made of the register width and processor clock, only a specific fixed number of possible operating frequencies can be produced.

Processor-clocked intermediate memories or buffer memories and logic circuits are provided in the drive logic for a control of the accesses onto the memory in conformity with the processor clock and access cycle.

Subsequently, the data d read by way of example in the sub-memory SRAM 0, 1 addressed by the second and third memory link addresses sfa 2, 3 is successively transferred to the processor MP via the intermediate memory ZSP in conformity with processor clock and access cycle.

During sleep the processor clock is shut off, and only the internal watchdog timer is running to periodically wake up the processor (about every 18ms).

Not only the processor clock is dependent on the reference clock, but also some other clock rates, such as the iGPU clock and memory clock, so you can use the increasement of the reference clock not only to increase the processor speed of an APU with a locked multiplier.

As an alternative to this it is possible to use, for example, a processor clock pulse, by determining the number of processor cycles between the instant at which the search commenced and the current instant.

In a further development of the invention, the waking signal issued by the waking circuit, preferably the comparator, is fed to an interrupt-input of the microprocessor such that it can also be woken up from a deep energy saving mode in which, for example, the processor clock and the processor interfaces are deactivated.