Translation of "Memory cycle" in German

The memory requirements per cycle do not change in principle, even without pre-processing of the data.

A refreshing of all memory cells in each memory cycle is generally neither necessary nor economical.

With such an operating mode, the stored information is first read out at each memory cycle and may be changed, if desired, before renewed inscription of the information.

The storage of the new actual value amplitude occurs when the memory cycle of the memory 33 has once sequenced and is again at its specific initial value.

During the course of the previously mentioned memory cycle in the counter reading memory ZSP1 for interrogating the individual momentary second counter readings, the only thing to be done is to check whether an overflow bit is stored with the respective memory second counter reading.

The first solution of this problem has the disadvantage that the maximum data clock frequency can be only half as high as the maximum memory cycle frequency.

The first solution of this problem has the advantage that the maximum data clock frequency can only be half as high as the maximum memory cycle frequency.

The first solution of this problem is the disadvantage that the maximum data clock frequency can only be half as high as the maximum memory cycle frequency.

Since the internal data lines are largely decoupled from the external data line so that no external noise can penetrate into the memory, the cycle time of the memory depends mainly on the internal parasitic capacities.

An asynchronous clock circuit 6 is provided for this purpose, which generates an asynchronous computer clock cycle, namely corresponding to the duration of a memory cycle.

Upon the first actuation of the selector the parameters assigned to the single serving of the beverage are loaded into a working memory and the cycle is started.

At the beginning of such a memory cycle, the following signal conditions are present at the inputs of the semiconductor memory for the corresponding control signals: R/W and CAS are already at "Low", and RAS goes to "Low".

Since the counter arrangement Z2 continuously offers address signals, an interrogation and subsequent conversion into the starting counter reading occurs for all second counter readings stored in the counter reading memory ZSP1 during the course of a memory cycle extending over a plurality of message cells or respectively dummy cells.

The second time interval s is variable and therefore potentially lasts, for example, between 0 and 5 ?s and the memory cycle 1/2/3/4 is intended to immediately trigger another refresh cycle 5 or 5 in the second time interval s.

However, when no memory cycle 1/2/3/4 occurred within the second time interval s, for example, after the resetting of the trigger circuit 19, then the trigger circuit is reset this time via the pulse of the curve e in FIG. 4 supplied by the timer 20 and by the AND gates 15 and 16 and the trigger circuits 17 and 18. In the illustrated example, this occurs at about 16 ?s after the beginning a' of the most recently preceding, first time interval r. This is slightly delayed until approximately the beginning of the next first time interval r, after which the trigger circuit 13 can no longer supply a refresh cycle clock 5 or 5 to the AND gate 21 in the subsequently-following first time interval r.

The first solution of this problem has the disadvantage that the maximum data clock frequency can only be half as great as the maximum memory cycle frequency.

In the known RAM memory units, no access from the exterior, i.e., from an externally-connected processor, to the appertaining RAM memory unit is permitted during the duration of a refresh cycle, i.e., no normal memory cycle is executed, such as a read cycle or a write cycle.

With respect to memory accesses, a cycle of permissible program addresses ad is stipulated, which cycle takes into account that a number m of the four processors 0 - 3 may access the memory area MX.